This invention relates to semiconductor integrated circuit devices and more particularly to an output contact arrangement for integrated logic circuit devices.
Integrated injection logic, also known as merged transistor logic, is a well-known form of logic device as embodied in semiconductor bipolar integrated circuits. The basic logic unit as originally proposed and implemented comprises an inverter implemented as a multicollector NPN transistor. Base drive is supplied by injection from the emitter of a lateral PNP transistor whose collector is merged with the base of the NPN transistor. The PNP transistor may be of the vertical type in the configuration referred to as substrate fed logic. However, in any of the variations, the collector of the PNP and the base of the NPN and the base of the PNP and emitter of the NPN are merged. Logic functions are obtained by direct coupling of transistors.
In a particular form of integrated injection logic termed Schottky I.sup.2 L, Schottky diodes are provided in series with the collector output or outputs. These diodes have the effect both of reducing the signal swing and reducing the downward, inverse, current gain. The former improves the power-delay efficiency and the latter the intrinsic speed limit.
However, although the Schottky I.sup.2 L configuration is highly advantageous where the outputs are connected to other I.sup.2 L units to form logic arrays, it is disadvantageous when the output connects to other non-logic circuitry. In particular, the Schottky output has a high saturation voltage comprised of the voltage drop across the Schottky junction in addition to the intrinsic saturation voltage of the NPN transistor. Accordingly, output transistors normally have conventional ohmic, or low resistance, contacts to the collector thereby providing a low saturation voltage by virtue of the low resistance contact and the high downward, inverse, current gain. However, such output transistors with these characteristics suffer longer carrier storage delay times, thus limiting circuit speed.
Thus, an object of this invention is an output configuration having a desirably low output saturation voltage combined with minimal minority carrier storage to provide advantageously short signal propagation delays.